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MT8979 CEPT PCM 30/CRC-4 Frame & Interface
Data Sheet Features
* * * * * * * * * * Single chip primary rate 2048 kbit/s CEPT transceiver with CRC-4 option Meets CCITT Recommendation G.704 Selectable HDB3 or AMI line code Tx and Rx frame and multiframe synchronization signals Two frame elastic buffer with 32 sec jitter buffer Frame alignment and CRC error counters Insertion and detection of A, B, C, D signalling bits with optional debounce On-chip attenuation ROM with option for ADI codecs Per channel, overall and remote loop around ST-BUS compatible Ordering Information
MT8979AE 28 Pin PDIP MT8979AP 44 Pin PLCC MT8979APR 44 Pin PLCC MT8979AE1 28 Pin PDIP* MT8979AP1 44 Pin PLCC* MT8979APR1 44 Pin PLCC* *Pb Free Matte Tin Tubes Tubes Tape & Reel Tubes Tubes Tape & Reel
February 2005
ISO-CMOS ST-BUSTM Family
-40C to +85C
Description
The MT8979 is a single chip CEPT digital trunk transceiver that meets the requirements of CCITT Recommendation G.704 for digital multiplex equipment. The MT8979 is fabricated in Zarlink's low power ISOCMOS technology.
Applications
* * * * Primary rate ISDN network nodes Multiplexing equipment Private network: PBX to PBX links High speed computer to computer links
TxMF C2i F0i RxMF DSTi DSTo ADI CSTi0 CSTi1 CSTo
VDD ST-BUS Timing Circuitry Digital Attenuator ROM 2 Frame Elastic Buffer with Slip Control CEPT Link Interface RxD Remote & Digital Loopbacks RxA RxB TxA TxB
PCM/Data Interface
Serial Control Interface
ABCD Bit RAM
Phase Detector XCtl XSt Control Logic
CEPT Counter
E2i E8Ko VSS
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT8979
Data Sheet
28 PIN PDIP
Figure 2 - Pin Connections Pin Description Pin #
DIP PLCC
Name TxA TxB DSTo NC RxA RxB RxD CSTi1 NC NC
Description Transmit A (Output): A split phase unipolar signal suitable for use with TxB and an external line driver and transformer to construct the bipolar line signal. Transmit B (Output:) A split phase unipolar signal suitable for use with TxA and an external line driver and transformer to construct the bipolar line signal. Data ST-BUS (Output): A 2048 kbit/s serial output stream which contains the 30 PCM or data channels received from the CEPT line. No Connection. Receive A (Input): Received split phase unipolar signal decoded from a bipolar line receiver. Receive B (Input): Received split phase unipolar signal decoded from a bipolar line receiver. Received Data (Input): Input of the unipolar data generated from the line receiver. This data may be NRZ or RZ. Control ST-BUS Input #1: A 2048 kbit/s stream that contains channel associated signalling, frame alignment and diagnostic functions. No Connection. No Connection.
1 2 3 4 5 6 7 8 9 10
2 3 5 4 9 10 11 13
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Zarlink Semiconductor Inc.
VSS CSTi0 E8Ko NC VSS XCtl XSt NC CSTo NC DSTi 44 PIN PLCC
TxA TxB DSTo NC RxA RxB RxD CSTi1 NC NC ADI CSTi0 E8Ko VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD IC F0i E2i NC RxMF TxMF C2i NC DSTi NC CSTo XSt XCtl
NC NC RxA RxB RxD NC CSTi1 NC NC NC ADI
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28
VSS DSTo NC TxB TxA VDD IC NC F0i NC E2i NC RxMF TxMF NC NC C2i NC NC NC NC NC
MT8979
Pin Description (continued) Pin #
DIP PLCC
Data Sheet
Name ADI
Description Alternate Digit Inversion (Input): If this input is high, the CEPT timeslots which are specified on CSTi0 as voice channels are ADI coded and decoded. When this bit is low it disables ADI coding for all channels. This feature allows either ADI or non-ADI codecs to be used on DSTi and DSTo. Control ST-BUS Input #0: A 2048 kbit/s stream that contains 30 per channel control words and two Master Control Words. Extracted 8 kHz Clock (Output): An 8 kHz output generated by dividing the extracted 2048 kHz clock by 256 and aligning it with the received CEPT frame. The 8 kHz signal can be used for synchronizing the system clock to the extracted 2048 kHz clock. Only valid when device achieves synchronization (goes low during a loss of signal or a loss of basic frame synchronization condition). E8Ko goes high impedance when 8 kHzSEL = 0 in MCW2. External Control (Output): An uncommitted external output pin which is set or reset via bit 1 in Master Control Word 2 on CSTi0. The state of XCtl is updated once per frame. External Status: The state of this pin is sampled once per frame and the status is reported in bit 1 of the Master Status Word 1 on CSTo. Control ST-BUS Output: A 2048 kbit/s serial control stream which provides the 16 signalling words, two Master Status Words, Phase Status Word and CRC Error Count. No Connection. Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the 30 PCM or data channels to be transmitted on the CEPT trunk. No Connection. 2048 kbit/s System Clock (Input): The master clock for the ST-BUS section of the chip. All data on the ST-BUS is clocked in on the falling edge of the C2i and output on the rising edge. The falling edge of C2i is also used to clock out data on the CEPT transmit link. Transmit Multiframe Boundary (Input): This input can be used to set the channel associated and CRC transmitted multiframe boundary (clear the frame counters). The device will generate its own multiframe if this pin is held high. Received Multiframe Boundary (Output): An output pulse delimiting the received Multiframe boundary. (This multiframe is not related to the received CRC multiframe.) The next frame output on the data stream (DSTo) is received as frame 0 on the CEPT link. No Connection. Extracted 2048 kHz Clock (Input): The falling edge of this 2048 kHz clock is used to latch the received data (RxD). This clock input must be derived from the CEPT received data and must have its falling edge aligned with the center of the received bit (RxD).
11
17
12 13
19 20
CSTi0 E8Ko
15
23
XCtl
16 17 18 19 20 21
24 26
XSt CSTo NC
28
DSTi NC
34
C2i
22
37
TxMF
23
38
RxMF
24 25 40
NC E2i
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Zarlink Semiconductor Inc.
MT8979
Pin Description (continued) Pin #
DIP PLCC
Data Sheet
Name F0i IC VDD VSS
Description Frame Pulse Input: The ST-BUS frame synchronization signal which defines the beginning of the 32 channel frame. Internal Connection: Tie to VSS (Ground) for normal operation. Positive Power Supply Input (+5 Volts). Negative Power Supply Input (Ground).
26 27 28 14
42 44 1 6,8, 22
Functional Description
The MT8979 is a CEPT trunk digital link interface conforming to CCITT Recommendation G.704 for PCM 30 and I.431 for ISDN. It includes features such as: insertion and detection of synchronization patterns, optional cyclical redundancy check and far end error performance reporting, HDB3 decoding and optional coding, channel associated or common channel signalling, programmable digital attenuation and a two frame received elastic buffer. The MT8979 can also monitor several conditions on the CEPT digital trunk, which include, frame and multiframe synchronization, received all 1's alarms, data slips as well as framing and CRC errors, both near and far end. The system interface to the MT8979 is a TDM bus structure that operates at 2048 kbit/s known as the ST-BUS. This serial stream is divided into 125 s frames that are made up of 32 x 8 bit channels. The line interface to the MT8979 consists of split phase unipolar inputs and outputs which are supplied from/to a bipolar line receiver/driver, respectively.
2.0 ms Frame 15 Frame 0
********
Timeslot 0 Timeslot 1
Frame 14
Frame 15
Frame 0
****
125 s Bit 4 Bit 5 Bit 6 Bit 7
Timeslot 30
Timeslot 31
Most Significant Bit (First)
Bit 1
Bit 2
Bit 3
Bit 8
Least Significant Bit (Last)
(8/2.048) s
Figure 3 - CEPT Link Frame & Multiframe Format
CEPT Interface
The CEPT frame format consists of 32, 8 bit timeslots. Of the 32 timeslots in a frame, 30 are defined as information channels, timeslots 1-15 and 17-31 which correspond to telephone channels 1-30. An additional voice/data channel may be obtained by placing the device in common channel signalling mode. This allows use of timeslot 16 for 64 kbit/s common channel signalling.
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Zarlink Semiconductor Inc.
MT8979
Data Sheet
Synchronization is included within the CEPT bit stream in the form of a bit pattern inserted into timeslot 0. The contents of timeslot 0 alternate between the frame alignment pattern and the non-frame alignment pattern as described in Figure 4. Bit 1 of the frame alignment and non-frame alignment bytes have provisions for additional protection against false synchronization or enhanced error monitoring. This is described in more detail in the following section. In order to accomplish multiframe synchronization, a 16 frame multiframe is defined by sending four zeros in the high order quartet of timeslot 16 frame 0, i.e., once every 16 frames (see Figure 5). The CEPT format has four signalling bits, A, B, C and D. Signalling bits for all 30 information channels are transmitted in timeslot 16 of frames 1 to 15. These timeslots are subdivided into two quartets (see Table 6). Bit Number 1
Timeslot 0 containing the frame alignment signal Timeslot 0 containing the nonframe alignment signal Reserved for International use (1) Reserved for International use (2)
2
0
3
0
4
1
5
1
6
0
7
1
8
1
1
Alarm indication to the remote PCM multiplex equipment
See Note #3
See Note #3
See Note #3
See Note #3
See Note #3
Figure 4 - Allocation of Bits in Timeslot 0 of the CEPT Link
Note 1 : With CRC active, this bit is ignored. Note 2 : With SiMUX active, this bit transmits SMF CRC results in frames 13 and 15 Note 3 : Reserved for National use
.
Timeslot 16 of frame 0
Timeslot 16 of frame 1
ABCD bits for telephone channel 1 (timeslot 1) ABCD bits for telephone channel 16 (timeslot 17)
Timeslot 16 of frame 15
0000
XYXX
***
ABCD bits for telephone channel 15 (timeslot 15)
ABCD bits for telephone channel 30 (timeslot 31)
Figure 5 - Allocation of Bits in Timeslot 16 of the CEPT Link Cyclic Redundancy Check (CRC) An optional cyclic redundancy check (CRC) has been incorporated within CEPT bit stream to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability. The CRC process treats the binary string of ones and zeros contained in a submultiframe (with CRC bits set to binary zero) as a single long binary number. This string of data is first multiplied by x4 then divided by the generating polynomial x4+x+1. This division process takes place at both the transmitter and receiver end of the link. The remainder calculated at the receiver is compared to the one received with the data over the link. If they are the same, it is of high probability that the previous submultiframe was received error free. The CRC procedure is based on a 16 frame multiframe, which is divided into two 8 frame submultiframes (SMF). The frames which contain the frame alignment pattern contain the CRC bits, C1 to C4 respectively, in the bit 1 position. The frames which contain the non-frame alignment pattern contain within the bit 1 position, a 6 bit CRC multiframe alignment signal and two spare bits (in frames 13 and 15), which are used for CRC error performance reporting (refer to Figure 6). During the CRC encoding procedure the CRC bit positions are initially set at zero. The remainder of the calculation is stored and inserted into the respective CRC bits of the next SMF. The decoding process repeats the multiplication division process and compares the remainder with the CRC bits received in the next SMF.
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Zarlink Semiconductor Inc.
MT8979
Data Sheet
The two spare bits (denoted Si1 and Si2 in Figure 6) in the CRC-4 multiframe are used to monitor far-end error performance. The results of the CRC-4 comparisons for the previously received SMFII and SMFI are encoded and transmitted back to the far end in the Si bits (refer to Table 1).
Si1 bit (frame 13) 1 1 0 0
Si2 bit (frame 15) 1 0 1 0
Meaning
CRC results for both SMFI, II are error free. CRC result for SMFII is in error. CRC result for SMFI is error free. CRC result for SMFII is error free. CRC result for SMFI is in error. CRC results for both SMFI, II are in error.
Table 1 - Coding of Spare Bits Si1 and Si2 Multiple Frame Component CRC Frame #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Frame Type
Frame Alignment Signal Non-Frame Alignment Signal
Timeslot Zero 1
C1 0 C2 0 C3 1 C4 0 C1 1 C2 1 C3 Si1 Si2
(3)
2
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
3
0 A(1) 0 A
(1)
4
1 Sn(2) 1 Sn
(2)
5
1 Sn(2) 1 Sn
(2)
6
0 Sn(2) 0 Sn
(2)
7
1 Sn(2) 1 Sn
(2)
8
1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2)
S M F I
Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal
0 A(1) 0 A A
(1)
1 Sn(2) 1 Sn Sn
(2)
1 Sn(2) 1 Sn Sn
(2)
0 Sn(2) 0 Sn Sn
(2)
1 Sn(2) 1 Sn Sn
(2)
0
(1)
1
(2)
1
(2)
0
(2)
1
(2)
S M F I I
Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal
0 A(1) 0 A A
(1)
1 Sn(2) 1 Sn Sn
(2)
1 Sn(2) 1 Sn Sn
(2)
0 Sn(2) 0 Sn Sn
(2)
1 Sn(2) 1 Sn Sn
(2)
C4
(3)
0
(1)
1
(2)
1
(2)
0
(2)
1
(2)
Figure 6 - CRC Bit Allocation and Submultiframing
Note 1 : Remote Alarm. Keep at 0 for normal operation. Note 2 : Reserved for National use. Keep at 1 for normal operation. Note 3 : Used to monitor far-end CRC error performance.
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Zarlink Semiconductor Inc.
MT8979
125s CHANNEL 31 CHANNEL 0
Data Sheet
***
BIT 7 BIT 6 BIT 5 BIT 4
CHANNEL 30
CHANNEL 31
CHANNEL 0
Most Significant Bit (First)
BIT 3
BIT 2
BIT 1
BIT 0
Least Significant Bit (Last)
(8/2.048)s
Figure 7 - ST-BUS Stream Format
ST-BUS Interface
The ST-BUS is a synchronous time division multiplexed serial bus with data streams operating at 2048 kbit/s and configured as 32, 64 kbit/s channels (refer Figure 7). Synchronization of the data transfer is provided from a frame pulse, which identifies the frame boundaries and repeats at an 8 kHz rate. Figure 17 shows how the frame pulse (F0i) defines the ST-BUS frame boundaries. All data is clocked into the device on the falling edge of the 2048 kbit/s clock (C2i), while data is clocked out on the rising edge of the 2048 kbit/s clock at the start of the bit cell. Data Input (DSTi) The MT8979 receives information channels on the DSTi pin. Of the 32 available channels on this serial input, 30 are defined as information channels. They are channels 1-15 and 17-31. These 30 timeslots are the 30 telephone channels of the CEPT format numbered 1-15 and 16-30. Timeslot 0 and 16 are unused to allow the synchronization and signalling information to be inserted, from the Control Streams (CSTi0 and CSTi1). The relationship between the input and output ST-BUS stream and the CEPT line is illustrated in Figures 8 to 12. In common channel signalling mode timeslot 16 becomes an active channel. In this mode channel 16 on DSTi is transmitted on timeslot 16 of the CEPT link unaltered. This mode is activated by bit 5 of channel 31 of CSTi0. Control Input 0 (CSTi0) All the necessary control and signalling information is input through the two control streams. Control ST-BUS input number 0 (CSTi0) contains the control information that is associated with each information channel. Each control channel contains the per channel digital attenuation information, the individual loopback control bit, and the voice or data channel identifier, see Table 2. When a channel is in data mode (B7 is high) the digital attenuation and Alternate Digit Inversion are disabled. It should be noted that the control word for a given information channel is input one timeslot early, i.e., channel 0 of CSTi0 controls channel 1 of DSTi. Channels 15 and 31 of CSTi0 contain Master Control Words 1 and 2, which are used to set up the interface feature as seen by the respective bit functions of Tables 3 and 4. Control Input 1 (CSTi1) Control ST-BUS input stream number 1 (CSTi1) contains the synchronization information and the A, B, C & D signalling bits for insertion into timeslot 16 of the CEPT stream (refer to Tables 5 to 8). Timeslot 0 contains the four zeros of the multiframe alignment signal plus the XYXX bits (see Figure 5). Channels 1 to 15 of CSTi1 contain the A, B, C & D signalling bits as defined by the CEPT format (see Figure 5), i.e., channel 1 of CSTi1 contains the A,B,C & D bits for DSTi timeslots 1 and 17. Channel 16 contains the frame alignment signal, and channel 17 contains the non-frame alignment signal (see Figure 4). Channel 18 contains the Master Control Word 3 (see Table 9). Figure 11 shows the relationship between the control stream (CSTi1) and the CEPT stream.
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Zarlink Semiconductor Inc.
MT8979
Control Output (CSTo)
Data Sheet
Control ST-BUS output (CSTo) contains the multiframe signal from timeslot 16 of frame 0 (see Table 10). Signalling bits A, B, C & D for each CEPT channel are sourced from timeslot 16 of frames 1-15 and are output in channels 115 on CSTo , as shown in Table 11. The frame alignment signal and nonframe alignment signal, received from timeslot 0 of alternate frames, are output in timeslots 16 and 17 as shown in Tables 12 and 13. Channel 18 contains a Master Status Word, which provides to the user information needed to determine the operating condition of the CEPT interface i.e., frame synchronization, multiframe synchronization, frame alignment byte errors, slips, alarms, and the logic of the external status pin (see Table 14). Figure 12, shows the relationship between the control stream channels and the CEPT signalling channels in the multiframe. The ERR bit in the Master Status word is an indicator of the number of errored frame alignment bytes that have been received in alternate timeslot zero. The time interval between toggles of the ERR bit can be used to evaluate the bit error rate of the line according to the CCITT Recommendation G.732 (see section on Frame Alignment Error Counter). Channel 19 contains the Phase Status Word (see Table 15), which can be used to determine the phase relationship between the ST-BUS frame pulse (F0i) and the rising edge of E8Ko. This information could be used to determine the long term trend of the received data rate, or to identify the direction of a slip. Channel 20 contains the CRC error count (see Table 16). This counter will wrap around once terminal count is achieved (256 errors). If the maintenance option is selected (bit 3 of MCW3) the counter is reset once per second. Channel 21 contains the Master Status Word 2 (see Table 17). This byte identifies the status of the CRC reframe and CRC sync. It also reports the Si bits received in timeslot 0 of frames 13 and 15 and the ninth and most significant bit (b8) of the 9-bit Phase Status Word.
Elastic Buffer
The MT8979 has a two frame elastic buffer at the receiver, which absorbs the jitter and wander in the received signal. The received data is written into the elastic buffer with the extracted E2i (2048 kHz) clock and read out of the buffer on the ST-BUS side with the system C2i (2048 kHz) clock (e.g., PBX system clock). Under normal operating conditions, in a synchronous network, the system C2i clock is phase-locked to the extracted E2i clock. In this situation every write operation to the elastic buffer is followed by a read operation. Therefore, underflow or overflow of data in the elastic buffer will not occur. If the system clock is not phase-locked to the extracted clock (e.g., lower quality link which is not selected as the clock source for the PBX) then the data rate at which the data is being written into the device on the line side may differ from the rate at which it is being read out on the ST-BUS side. When the clocks are not phase-locked, two situations can occur: Case #1: If the data on the line side is being written in at a rate SLOWER than it is being read out on the ST-BUS side, the distance between the write pointer and the read pointer will begin to decrease over time. When the distance is less than two channels, the buffer will perform a controlled slip which will move the read pointers to a new location 34 channels away from the write pointer. This will result in the REPETITION of the received frame. Case #2: If the data on the line side is being written in at a rate FASTER than it is being read out on the ST-BUS side, the distance between the write pointer and the read pointer will begin to increase over time. When the distance exceeds 42 channels, the elastic buffer will perform a controlled slip which will move the read pointer to a new location ten channels away from the write pointer. This will result in the LOSS of the last received frame. Note that when the device performs a controlled slip, the ST-BUS address pointer is repositioned so that there is either a 10 channel or 34 channel delay between the input CEPT frame and the output ST-BUS frame. Since the buffer performs a controlled slip only if the delay exceeds 42 channels or is less than two channels, there is a minimum eight channel hysteresis built into the slip mechanism. The device can, therefore, absorb eight channels or 32.5 s of jitter in the received signal.
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Zarlink Semiconductor Inc.
MT8979
Data Sheet
There is no loss of frame synchronization, multiframe synchronization or any errors in the signalling bits when the device performs a slip.
DSTi 0 Channel # CEPT Timeslot # 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 10 11 12 13 14 15 16 17 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31
9 10 11 12 13 14 15 CCS 17 18
Figure 8 - Relationship between Input DSTi Channels and Transmitted CEPT Timeslots
DSTi Channel # CEPT Timeslot # 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 11 12 13 14 15 10 11 12 13 14 15 16 SIG 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31
Figure 9 - Relationship between Received CEPT Timeslots and Output DSTo Channels
CSTi0 0 Channel # Device Control CEPT Channel # 1 Control Word 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1
2
3
4
5
6
7
8
9 10 11 12 13 14
15 C1
16 17 18 19 20 21 22 23 24 25 26
27
28
29
30
31 C2
17 18 19 20 21 22 23 24 25 26 27
28
29
30
31
Figure 10 - Relationship between Input CSTi0 Channels and Controlled CEPT Timeslots
CSTi1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Channel # Device C3 * * * * * * * * Control CEPT FRAME # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A N CHANNEL # 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 0 0 27 * 28 * 29 * 30 * 31 *
Figure 11 - Relationship between Input CSTi1 Channels and Transmitted CEPT Frames
CSTo Channel # Device Status CEPT FRAME # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A TIMESLOT # 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 0 N 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 S1 S2 S3 S4 * * * * * * * * * *
Figure 12 - Relationship between Received CEPT Frames and Output CSTo Channels
- *Denotes Unused Channel (CSTo output is not put in high impedance state) A Denotes Frame-Alignment Frame N Denotes Non Frame-Alignment Frame C1, C2, C3 Denotes Master Control Words 1,2,3 SIG Denotes Signalling Channel -CCS Denotes Signalling Channel if Common Channel Signalling Mode Selected -S1 Denotes Master Status Word 1 (MSW1) -S2 Denotes Phase Status Word (PSW) -S3 Denotes CRC Error Count -S4 Denotes Master Status Word 2 (MSW2)
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Zarlink Semiconductor Inc.
MT8979
Frame Alignment Error Counter
Data Sheet
The MT8979 provides an indication of the bit error rate found on the link as required by CCITT Recommendation G.703. The ERR bit (Bit 5 of MSW1) is used to count the number of errors found in the frame alignment signal and this can be used to estimate the bit error rate. The ERR bit changes state when 16 errors have been detected in the frame alignment signal. This bit can not change state more than once every 128 ms, placing an upper limit on the detectable error rate at approximately 10-3. The following formula can be used to calculate the BER: BER= 16* number of times ERR bit toggles 7 * 4000 * elapsed time in seconds
where: 7 - is the number of bits in the frame alignment signal (0011011). 16 - is the number of errored frame alignment signals counted between changes of state of the ERR bit. 4000 - is the number of frame alignment signals in a one second interval. This formula provides a good approximation of the BER given the following assumptions: 1. The bit errors are uniformly distributed on the line. In other words, every bit in every channel is equally likely to get an error. 2. The errors that occur in channel 0 are bit errors. If the first assumption holds and the bit error rate is reasonable, (below 10-3) then the probability of two or more errors in seven bits is very low.
Attenuation ROM
All transmit and receive data in the MT8979 is passed through the digital attenuation ROM according to the values set on bits 5 - 0 of data channels in the control stream (CSTi0). Data can be attenuated on a per-channel basis from 1 to -6 dB for both Tx and Rx data (refer Table 2). Digital attenuation is applied on a per-channel basis to the data found one channel after the control information stored in the control channel CSTi0, i.e., control stream 0 channel 4 contains the attenuation setting for data stream (DSTo) channel 5.
Signalling Bit RAM
The A, B, C, & D Bit RAM is used to retain the status of the per-channel signalling bits so that they may be multiplexed into the Control Output Stream (CSTo). This signalling information is only valid when the module is synchronized to the received data stream. If synchronization is lost, the status of the signalling bits will be retained for 6.0 ms provided the signalling debounce is active. Integrated into the signalling bit RAM is a debounce circuit which will delay valid signalling bit changes for 6.0 to 8.0 ms. By debouncing the signalling bits, a bit error will not affect the call in progress. (See Table 3, bits 3-0 of channel 15 on the CSTi0 line.)
CEPT PCM 30 Format MUX
The CEPT Link Multiplexer formats the data stream corresponding to the CEPT PCM 30 format. This implies that the multiplexer will use timeslots 1 to 15 and 17 to 31 for data and uses timeslots 0 & 16 for the synchronization and channel associated signalling. The frame alignment or non-frame alignment signals for timeslot zero are sourced by the control stream input CSTi1 channel 16 and 17, respectively. The most significant bit of timeslot zero will optionally contain the cyclical redundancy check, CRC multiframe pattern and Si bits used for far-end CRC monitoring.
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Zarlink Semiconductor Inc.
MT8979
Framing Algorithms
Data Sheet
There are three distinct framers within the MT8979. These include a frame alignment signal framer, a multiframe framer and a CRC framer. Figure 13 shows the state diagram of the framing algorithms. The dotted lines shows optional features, which are enabled in the maintenance mode. The frame synchronization circuit searches for the first frame alignment signal within the bit stream. Once detected, the frame counters are set to find the non-frame alignment signal. If bit 2 of the non-frame alignment signal is not one, a new search is initiated, else the framer will monitor for the frame alignment in the next frame. If the frame alignment signal is found, the device immediately declares frame synchronization. The multiframe synchronization algorithm is dependent upon the state of frame alignment framer. The multiframe framer will not initiate a search for multiframe synchronization until frame sync is achieved. Multiframe synchronization will be declared on the first occurrence of four consecutive zeros in the higher order quartet of channel 16. Once multiframe synchronization is achieved, the framer will only go out of synchronization after detection of two errors in the multiframe signal or loss of frame alignment synchronization. The CRC synchronization algorithm is also dependent on the state of the frame alignment framer, but is independent of the multiframe synchronization. The CRC framer will not initate a search for CRC framing signal until frame alignment synchronization is achieved. Once frame alignment synchronization is acquired, the CRC framer must find two framing signals in bit 1 of the non-frame alignment signal. Upon detection of the second CRC framing signal the MT8979 will immediately go into CRC synchronization. When maintenance feature is enabled (maint bit = 1) the CRC framer will force a complete reframe of the device if CRC frame synchronization is not found within 8 ms or more than 914 CRC errors occur per second.
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Zarlink Semiconductor Inc.
MT8979
Data Sheet
out of synchronization No
search for frame alignment signal No Yes verify bit 2 of nonframe alignment signal Yes time out > 8ms verify second occurrence of frame alignment signal Yes frame synchronization acquired find two CRC frame alignment signals Yes CRC synchronization acquired
# of consecutive incorrect frame alignment signals = 3 No
number of CRC errors > 914/s
search for multiframe alignment signal Yes multiframe synchronization acquired
No
Yes - - - - - Only if the maintenance option is selected check for two errored multiframe alignment signals
No
Figure 13 - Synchronization State Diagram
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Zarlink Semiconductor Inc.
MT8979
Bit 7 Name DATA Description
Data Sheet
Data Channel: If `1`, then the controlled timeslot on the CEPT 2048 kbit/s link is treated as a data channel; i.e., no ADI encoding or decoding is performed on transmission or reception, and digital attenuation is disabled. If `0`, then the state of the ADI pin determines whether or not ADI encoding and decoding is performed. Per-Channel Loopback: If `1`, then the controlled timeslot on the transmitted CEPT 2048 kbit/s link is looped internally to replace the data on the corresponding received timeslot. If `0`, then this function is disabled. This function only operates if frame synchronization is received from the CEPT link. If more than one channel is looped per frame only the first one will be active. Receive Attenuation Pad: Per timeslot receive attenuation control bits. RXPAD4 0 0 0 0 1 1 1 1 RXPAD2 0 0 1 1 0 0 1 1 RXPAD1 0 1 0 1 0 1 0 1 Gain (dB) 0 -1 -2 -3 -4 -5 -6 1
6
LOOP
5,4,3
RXPAD4,2,1
2,1,0
TXPAD4,2,1
Transmit Attenuation Pad: Per timeslot transmit attenuation control bits. TXPAD4 0 0 0 0 1 1 1 1 TXPAD2 0 0 1 1 0 0 1 1 TXPAD1 0 1 0 1 0 1 0 1 Gain (dB) 0 -1 -2 -3 -4 -5 -6 1
Table 2 - Per Channel Control Word: Data Format for CSTi0 Channels 0-14, and 16-30
Bit 7 6
Name (N/A) LOOP16 Keep at `1` for normal operation.
Description
Channel 16 Loopback: If `1`, then timeslot 16 on the transmitted CEPT 2048 kbit/s link is looped internally to replace the data received on timeslot 16. If `0,` then this function is disabled. This function only operates if frame synchronization is received from the CEPT link and only a single timeslot can be looped within the frame. Keep at `1` for normal operation.
5,4 3,2, 1 &0
(N/A)
NDBD, NDBC, Signalling Bit Debounce: If `1`, then no debouncing is applied to the received A, B, C or NDBB D signalling bits. If `0`, then the received A, B, C or D signalling bits are debounced for & NDBA between 6 and 8 ms. Table 3 - Master Control 1 (MCW1): Data Format for CSTi0 Channel 15
13
Zarlink Semiconductor Inc.
MT8979
Bit 7 6 5 Name (N/A) (N/A) CCS Keep at `1` for normal operation. Keep at `0` for normal operation. Description
Data Sheet
Common Channel Signalling: If 1, then the MT8979 operates in its common channel signalling mode. Channel 16 on the DSTi pin is transmitted on timeslot 16 of the CEPT link, and timeslot 16 from the received CEPT link is output on channel 16 on the DSTo pin. Channel 15 on the CSTi0 pin contains the information for the control of timeslot 16. Channels 0 to 15 on CSTi1 and CSTo are unused. If `0`, the device is in channel associated signalling mode where channel 16 is used to transmit the ABCD signalling bits. 8KHz Select: If `1`, then an 8 kHz signal synchronized to the received CEPT 2048 kbit/s link is output on the E8Ko pin. This feature is only valid when frame synchronization is received from the CEPT link. If `0`, then the E8Ko pin goes into its high impedance state. Transmit Alarm Indication Signal: If `1`, then an all 1' s alarm signal is transmitted on all timeslots. If `0`, then the timeslots functions normally. Transmit Timeslot 16 Alarm Indication Signal: If `1`, then an all 1's alarm signal is transmitted on timeslot 16. If `0`, then timeslot 16 functions normally. External Control: If `1`, then the XCtl pin is driven high. If `0`, then the XCtl pin is driven low. (unused) Table 4 - Master Control 2 (MCW2): Data Format for CSTi0 Channel 31
4
8KHzSEL
3
TXAIS
2
TXTS16AIS
1
XCTL
0
(N/A)
Bit 7-4
Name MA1-4
Description Transmit Multiframe Alignment Bits 1 to 4: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 of frame 0 of the multiframe. They should be kept at `0` to allow multiframe alignment to be detected. This bit is transmitted on the CEPT 2048 kbit/s link in bit position 5 of timeslot 16 of frame 0 of the multiframe. It is a spare bit which should be kept at `1` if unused. This bit is transmitted on the CEPT 2048 kbit/s link in bit position 6 of timeslot 16 of frame 0 of the multiframe. It is used to indicate the loss of multiframe alignment to the remote end of the link. A `1` on this bit is the signal that multiframe alignment on the received link has been lost. A `0' indicates that multiframe alignment is detected. These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 7 and 8 respectively, of timeslot 16 of frame 0 of the multiframe. They are spare bits which should be kept at `1` if unused.
3 2
X1 Y
1,0
X2,X3
Table 5 - Multiframe Alignment Signal: Data Format for CSTi1 Channel 0 on the Transmitted CEPT Link
14
Zarlink Semiconductor Inc.
MT8979
Bit 7, 6, 5 &4 Name A(N), B(N), C(N) & D(N) Description
Data Sheet
Transmit Signalling Bits for Channel N: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 in frame N, and are the A, B, C and D signalling bits associated with telephone channel N. The value of N lies in the range 1 to 15 and refers to the channel on the CSTi1 channel from which the bits are sourced, the telephone channel with which the bits are associated and the frame on the CEPT link on which the bits are transmitted. For example, the bits input on the CSTi1 pin on channel 3 are associated with telephone channel 3, which is timeslot 3 of the CEPT link, and are transmitted on bits positions 1 to 4 of timeslot 16 in frame 3 of each multiframe on the CEPT link . If bits B, C or D are not used they should be given the values `1, 0` and `1` respectively. The combination `0000` for ABCD bits should not be used for telephone channels 1 to 15 as this would interfere with multiframe alignment. Transmit Signalling Bits for Channel N+15: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 5 to 8 of timeslot 16 in frame N, and are the A, B, C and D signalling bits associated with telephone channel N+15. The value of N lies in the range 1 to 15 and refers to both the channel on the CSTi1 stream where the bits are supplied and the frame on the CEPT link on which the bits are transmitted, and indirectly indicates the telephone channel with which the bits are are associated. For example, the bits input on the CSTi1 pin on channel 3 are associated with telephone channel 18, which is timeslot 19 of the CEPT link, and are transmitted in bits positions 5 to 8 of timeslot 16 in frame 3 of each multiframe on the CEPT link .
3, 2, 1 &0
A(N+15), B(N+15), C(N+15) & D(N+15)
Table 6 - Channel Associated Signalling: Data Format for CSTi1 Channels 1 to 15
Bit 7
Name IU0
Description International Use 0: When CRC is disabled, this bit is transmitted on the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of frame-alignment frames . It is reserved for international use and should be kept at `1' when not used. If CRC is enabled, this bit is not used. Transmit Frame Alignment Frame Bits 2 to 8: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 2 to 8 of timeslot 0 of frame-alignment frames. These bits form the frame alignment signal and should be set to `0011011`. Table 7 - Frame Alignment Signal: Data Format for CSTi1 Channel 16
6-0
FAF2-8
15
Zarlink Semiconductor Inc.
MT8979
Bit 7 Name IU1 Description
Data Sheet
International Use 1: When the CRC is disabled and SiMUX bit in MCW3 is disabled, this bit is transmitted on the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of non-framealignment frames . It is reserved for international use and should be kept at `1` when not used. If CRC is enabled and SiMUX is disabled, this bit is transmitted in bit 1 of timeslot 0 for frame 13 and 15. If both CRC and SiMUX are enabled, then this bit is not used. Transmit Non-Frame Alignment Bit: This bit is transmitted on the CEPT 2048 kbit/s link in bit position 2 of timeslot 0 of non-frame-alignment frames. In order to differentiate between frame-alignment frames and non-frame-alignment frames, this bit should be kept at `1`. Non-Frame Alignment Alarm: This bit is transmitted on the CEPT 2048 kbit/s link in bit position 3 of timeslot 0 of non-frame-alignment frames . It is used to signal an alarm to the remote end of the CEPT link. The bit should be set to `1` to signal an alarm and should be kept at `0` under normal operation. National Use: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 4 to 8 of timeslot 0 of non-frame-alignment frames . These bits are reserved for national use, and on crossing international borders they should be set to `1`.
6
NFAF
5
ALM
4-0
NU1-5
Table 8 - Non-Frame-Alignment Signal: Data Format for CSTi1 Channel 17
Bit 7 6
Name N/A SiMUX Keep at zero for normal operation.
Description
When set to `1', this bit will cause the SMFI CRC result to be transmitted in the next outgoing Si1 bit in frame 13 and the SMFII CRC result to be transmitted in the next outgoing Si2 bit in frame 15. Remote Loopback: respectively. If set the RxA and RxB signals are looped to TxB and TxA
5 4 3
RMLOOP HDB3en Maint
Enable HDB3 Encoding: A '1' will disable the HDB3 line coding and transmit the information transparently. Maintenance: A '1' will force a terminal reframe if the CRC multiframe synchro- nization is not achieved within 8 ms of frame synchronization. Reframe will also be generated if more than 914 CRC errors occur within a one second interval (CRC error counter is reset with every one second interval). A '0' will disable this option. Enable Cyclical Redundancy Check: A '1' will enable the CRC generation on the transmit data. A '0' will disable the CRC generator. The CRC receiver is always active regardless of the state of CRCen. Digital Loopack: When set, the transmitted signal is looped around from DSTi to DSTo. The normal received data is interrupted. Force Reframe: If set, for at least 1 frame, and then cleared the chip will begin to search for a new frame position when the chip detects the change in state from high to low. Only the change from high to low will cause a reframe, not a continuous low level.
2
CRCen
1 0
DGLOOP ReFR
Table 9 - Master Control Word 3 (MCW3): Data Format for CSTi1 Channel 18
16
Zarlink Semiconductor Inc.
MT8979
Bit 7-4 Name MA1-4 Description
Data Sheet
Receive Multiframe Alignment Bits 1 to 4: These are the bits which are received from the CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 of frame 0 of the multiframe. They should all be `0`. This is the bit which is received on the CEPT 2048 kbit/s link in bit position 5 of timeslot 16 of frame 0 of the multiframe. It is a spare bit which should be `1` if unused. It is not debounced. This is the bit which is received on the CEPT 2048 kbit/s link in bit position 6 of timeslot 16 of frame 0 of the multiframe. It is used to indicate the loss of multiframe alignment at the remote end of the link. A `1` on this bit is the signal that multiframe alignment at the remote end of the link has been lost. A `0` indicates that multiframe alignment is detected. It is not debounced. These are the bits which are received on the CEPT 2048 kbit/s link in bit positions 7 and 8 respectively, of timeslot 16 of frame 0 of the multiframe. They are spare bits which should be `1` if unused. They are not debounced.
3
X1
2
Y
1,0
X2,X3
Table 10 - Received Multiframe Alignment Signal: Data Format for CSTo Channel 0 Bit 7, 6, 5 &4 Name A(N), B(N), C(N) & D(N) Description Receive Signalling Bits for Channel N: These are the bits which are received from the CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 in frame N (frame #), and are the A, B, C and D signalling bits associated with telephone channel N. The value of N lies in the range 1 to 15 and refers to the channel on the CSTo stream on which the bits are output, the telephone channel with which the bits are associated and the frame on the CEPT link on which the bits are received. For example, the bits output on the CSTo stream on channel 3 are associated with telephone channel 3, which is timeslot 3 of the CEPT link, and are received on bits positions 1 to 4 of timeslot 16 in frame 3 of each multiframe on the CEPT link . If bits B, C or D are not used they should have the values `1, 0` and `1` respectively. The combination `0000` for ABCD bits should not be found for telephone channels 1 to 15 as this implies interference with multiframe alignment. Receive Signalling Bits for Channel N+ 15: These are the bits which are received from the CEPT 2048 kbit/s link in bit positions 5 to 8 of timeslot 16 in frame N, and are the A, B, C and D signalling bits associated with telephone channel N+15. The value of N lies in the range 1 to 15 and refers to both the channel on the CSTo stream where the bits are output and the frame on the CEPT link on which the bits are received, and indirectly indicates the telephone channel with which the bits are are associated. The associated channel is N+15. For example, the bits output on the CSTo stream on channel 3 are associated with telephone channel 18, which is timeslot 19 of the CEPT link, and are received on bits positions 5 to 8 of timeslot 16 in frame 3 of each multiframe on the CEPT link .
3, 2, 1 &0
A(N+15), B(N+15), C(N+15) & D(N+15)
Table 11 - Received Channel Associated Signalling: Data Format for CSTo Channels 1 to 15
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Zarlink Semiconductor Inc.
MT8979
Bit 7 Name IU0 Description
Data Sheet
International Use 0: This is the bit which is received from the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of frame-alignment frames . It is reserved for the CRC remainder or for international use. Frame Alignment Signal Bits 2 to 8: These are the bits which are received from the CEPT 2048 kbit/s link in bit positions 2 to 8 of timeslot 0 of frame-alignment frames. These bits form the frame alignment signal and should have the values of `0011011`.
6-0
FAF2-8
Table 12 - Received Frame Alignment Signal: Data Format for CSTo Channel 16 Bit 7 Name IU1 Description International Use 1: This is the bit which is received from the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of non-frame-alignment frames . It is reserved for the CRC framing or as international bits. Receive Non-Frame Alignment Bit: This is the bit which is received from the CEPT 2048 kbit/s link in bit position 2 of timeslot 0 of non-frame-alignment frames . This bit should be `1` in order to differentiate between frame-alignment frames and non-framealignment frames. Non-Frame Alignment Alarm: This is the bit which is received from the CEPT 2048 kbit/s link in bit position 3 of timeslot 0 of non-frame-alignment frames . It is used to signal an alarm from the remote end of the CEPT link. This bit should have the value `0` under normal operation and should go to `1 `to signal an alarm. National Use: These are the bits which are received on the CEPT 2048 kbit/s link in bit positions 4 to 8 of timeslot 0 of non-frame-alignment frames . These bits are reserved for national use, and on crossing international borders they should have the value `1`.
6
NFAF
5
ALM
4-0
NU1-5
Table 13 - Received Non-Frame Alignment Signal: Data Format for CSTo Channel 17 Bit 7 6 5 Name TFSYN MFSYN ERR Description Frame Sync: This bit goes to `1` to indicate a loss of frame alignment synchronization by the MT8979. It goes to `0` when frame synchronization is detected. Multiframe Sync: This bit goes to `1` to indicate a loss of multiframe synchronization by the MT8979. It goes to `0` when multiframe synchronization is detected. Frame Alignment Error: This bit changes state when 16 or more errors have been detected in the frame alignment signal. It will not change state more than once every 128 ms. Control Slip: This bit changes state when a slip occurs between the received CEPT 2048 kbit/s link and the 2048 kbit/s ST-BUS. Receive Alarm Indication Signal: This bit goes to `1` to signal that an all-ones alarm signal has been detected on the received CEPT 2048 kbit/s . It goes to '0' when the allones alarm signal is removed. Receive Timeslot 16 Alarm Indication Signal: This bit goes to `1` to signal that an allones alarm signal has been detected on channel 16 of the received CEPT 2048 kbit/s link. It goes to '0' when the all-ones alarm signal is removed. External Status: This bit contains the data sampled once per frame at the XS pin. (Unused).
4 3
SLIP RXAIS
2
RXTS16AIS
1 0
XS N/A
Table 14 - Master Status Word 1 (MSW1): Data Format for CSTo Channel 18
18
Zarlink Semiconductor Inc.
MT8979
Bit 7-3 2-0 Name TxTSC TxBTC Description
Data Sheet
Transmit Timeslot Count: The value of these five bits indicate the timeslot count between the ST-BUS frame pulse and the rising edge of E8Ko. Transmit Bit Count:The value of these three bits indicate the bit position within the timeslot count reported in TxTSC above.
Table 15 - Phase Status Word (PSW): Data Format for CSTo Channel 19 Bit 7-0 Name CERC Description CRC Error Counter: This byte is the CRC error counter. The counter will wrap around once it reaches FF count. If maintenance option is activated, the counter will reset after a one second interval. Table 16 - CRC Error Count: Data Format for CSTo Channel 20 Bit 7 6 5-4 3 2 Name Si2 Si1 NA CRCTimer CRCRef Description The received Si bit in frame 15 is reported in this bit. Si2 will be updated after each RxMF pulse (pin 23). The received Si bit in frame 13 is reported in this bit. Si1 will be updated after each RxMF pulse (pin 23). Unused. CRC Timer: Transition from 1 to 0 indicates the start of one second interval in which CRC errors are accumulated. This bit stays high for 8 ms. CRC Reframe: A '1' indicates that the receive CRC multiframe synchronization could not be found within the time out period of 8 ms after detecting frame synchronization. This bit will go low if CRCSync goes low or if Maintenance is not activated. CRC Sync: A '0' indicates that CRC multiframing has been detected. Frame Count: This is the ninth and most significant bit (b8) of the Phase Status Word (see Table 15). If the phase status word is incrementing, this bit will toggle when the phase reading exceeds ST-BUS channel 31, bit 7. If the phase word is decrementing, then this bit will toggle when the reading goes below ST-BUS channel 0, bit 0.
1 0
CRCSync FrmPhase
Table 17 - Master Status Word 2 (MSW2): Data Format for CSTo Channel 21
Applications
The MT8979 is only a link interface to the CEPT trunk. As such, an external line driver and receiver is required along with an appropriate pulse transformer before being connected to the line. Transmitter In order to generate a bipolar line signal, the link interface to the MT8979 provides the user with two bipolar steering outputs, TxA and TxB. These correspond to the required positive and negative pulses on the transmission line. Figure 14 shows a recommended output circuit for driving a line pulse transformer.
19
Zarlink Semiconductor Inc.
MT8979
Data Sheet
The transistors are driven into saturation when they are turned on, which applies a step function to the transformer. The step input to the transformer produces a nearly constant di/dt before the current reaches steady state. By operating in the transient portion of the inductance response, the secondary of the transformer produces an almost square pulse. The base terminal of the transistors is AC coupled to the MT8979 so that there is no DC path from VDD to ground.
TxA
* * *
* * * *
+12V
*
1.:
:.5
33H MT8979
* TIPo
47F
1.:
TxB
* RINGo
Figure 14 - Bipolar Line Driver Receiver The receive line interface circuit shown in Figure 15 will decode the HDB3 line signals into two split phase unipolar steering signals. These signals are used to drive the violation detectors RxA and RxB as well as being NAND`ed to produce the received data (RxD). The NAND gate was removed from the devices to make the delay for the data path equal to the delay of the clock path. This will optimize the jitter performance of the receiver. The typical connection diagram for the CEPT digital trunk interface is provided in Figure 16. The bipolar line driver and receiver have been simplified for convenience as well as the addition of a clock extractor and phase-lock loop. The clock extractor is required to adjust the phase of the E2 clock in order to sample the received data in the middle of the pulse on RxD. The phase-lock loop, on the other hand, will correct the system clocks to absorb the low rate wander present on the line. Please note: The configuration shown in Figure 16 using the MT8940 may not meet some international standards for jitter performance. In cases where strict idle jitter specifications must be met, a custom phase-lock loop may be required.
20
Zarlink Semiconductor Inc.
MT8979
Data Sheet
* +5V *
RxT 1: RxR :1 :1
MT8979 RxA 74LS00 RxD
*
*
* +5V * *
*
RxB
Figure 15 - Typical Bipolar Line Receiver
VDD MT8980 STo0 STi0 STo1 STo2 STi1 F0i C4i MT8979 TxMF DSTi TxA DSTo CSTo0 CSTi1 CSTo TxB VDD
Line Driver
*
F0i C2i E8Ko
RxA RxD RxB
*
Line Receiver
MT8940 C4b F0b
E2i
P
Clock Extractor 16.388 Crystal
Figure 16 - Typical Connection Diagram
21
Zarlink Semiconductor Inc.
MT8979
Absolute Maximum Ratings* - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3 4 5 6 7 Supply Voltage Voltage at Digital Inputs Current at Digital Inputs Voltage at Digital Outputs Current at Digital Outputs Storage Temperature Package Power Dissipation Symbol VDD VI II VO IO TST P -65 -0.3 Min. -0.3 -0.3 Max. 7
Data Sheet
Units V V mA V mA C mW
VDD + 0.3 30 VDD + 0.3 30 150 800
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 Operating Temperature Supply Voltage Input Voltage High Input Voltage Low Sym. TOP VDD VH VL Min. -40 4.5 2.4 VSS 5 Typ. Max. 85 5.5 VDD 0.4 Units C V V V For 400 mV noise margin For 400 mV noise margin Test Conditions
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 Power Dissipation Supply Current Input High Voltage Input Low Voltage Input Leakage Output High Voltage Output High Current Output Low Voltage Output Low Current High Impedance Leakage Sym. P IDD VIH VIL IIL VOH IOH VOL IOL IOZ 2.4 7 VSS 2 10 1 10 20 0.4 2.0 0 1 Min. Typ. 40 8 Max. 88 16 VDD 0.8 10 VDD Units mW mA V V mA V mA V mA mA VI = 0 to VDD IOH=7 mA @ VOH=2.4 V Source VOH=2.4 V IOL=2 mA @ VOL= 0.4 V Sink VOL=0.4 V VO = 0 to VDD Test Conditions Outputs unloaded Outputs unloaded
Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
22
Zarlink Semiconductor Inc.
MT8979
AC Electrical Characteristics - Capacitances Characteristics 1 2 Input Pin Capacitance Output Pin Capacitance Sym. CI CO Min. Typ. 8 8 Max Units pF pF
Data Sheet
Test Conditions
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - ST-BUS Timing (Figures 17 and 18) Characteristics 1 2 3 4 5 6 7 8 9
*
Sym. tP20 tW20 tFPS tFPH tFPW tSOD tSIS tSIH tFPS2
Min. 400 200 50 50 100
Typ. 488 244
Max. 600
Units ns ns
Test Conditions
C2i Clock Period C2i Clock Width High or Low Frame Pulse Setup Time Frame Pulse Hold Time Frame Pulse Width Serial Output Delay Serial Input Setup Time Serial Input Hold Time Frame Pulse Setup Time 2
tP20 = 488 ns
150
ns ns
300 150*
ns ns ns ns ns 150 pF Load
30 55 20
Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. tSOD = 125 ns (max) over 0 - 70C temperature range.
F0i
C2i
ST-BUS BIT CELLS
Channel 31 Bit 0
Channel 0 Bit 7
Channel 0 Bit 6
Figure 17 - Clock and Frame Alignment for 2048 kbit/s ST-BUS Streams
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Zarlink Semiconductor Inc.
MT8979
Data Sheet
ST-BUS Bit Stream tFPW
Bit Cell
F0i
VIH VIL tFPS VIH
tFPH
tFPS2
tP20 tW20 tW20
C2i
VIL tSIS tSIH
DSTi VIH or CSTi0/1 VIL tSOD DSTo or CSTo VOH VOL
Figure 18 - Clock and Frame Timing for 2048 kbit/s ST-BUS Streams AC Electrical Characteristics - Multiframe Clock Timing (Figure 21) Characteristics 1 2 3 4 Receive Multiframe Output Delay Transmit Multiframe Setup Time Transmit Multiframe Hold Time Tx Multiframe to C2 Setup Time Sym. tRMFD tTMFS tTMFH tMF2S 50 50 100 * Min. Typ. Max. 150 Units ns ns ns ns Test Conditions 50 pF
Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * 256 tP20 - 100 ns Frame 15 DSTo Bit Cells F0i Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Bit 7 Bit 6 Frame 0 Bit 5 Bit 4 Bit 0 Bit 7
C2i
RxMF
Figure 19 - Functional Timing for Receive Multiframe Clocks
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Zarlink Semiconductor Inc.
MT8979
Frame N DSTi Bit Cells F0i Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Bit 7 Bit 6 Bit 5 Frame 0 Bit 4
Data Sheet
Bit 0
Bit 7
C2i
TxMF
Figure 20 - Functional Timing for Transmit Multiframe Clock
F0i tRMFD
C2i tRMFD
RxMF(1) tMF2S
tTMFS TxMF(1)
tTMFH
Figure 21 - Clock and Frame Timing for 2048 kbit/s ST-BUS Streams
Note 1: These two signals do not have a defined phase relationship.
AC Electrical Characteristics - XCtl, XS and E8Ko (Figures 22, 23 and 24) Characteristics 1 2 3 4 5 6 7 External Control Delay External Status Setup Time External Status Hold Time E8Ko Output Delay E8Ko Output Low Width E8Ko Output High Width E8Ko Output Transition Time Sym. tXCD tXSS tXSH t8OD t8OL t8OH t8OT 62.5 62.5 20 50 50 150 Min. Typ. Max. 100 Units ns ns ns ns ms ms ns 50 pF load 50 pF load 50 pF load 50 pF load Test Conditions 50 pF load
Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
25
Zarlink Semiconductor Inc.
MT8979
Data Sheet
F0i
VIH VIL
XCtl
VOH VOL tXCD
Figure 22 - XCtl Timing
ST-BUS Bit Cell Boundary Between Bit 3 Channel 17 and Bit 2 Channel 17
C2i
VIH VIL
XS
VIH VIL tXSS tXSH
Figure 23 - XS Timing
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Zarlink Semiconductor Inc.
MT8979
Data Sheet
Received CEPT Bits
Timeslot 0 Bit 4
***
Timeslot 16 Bit 4
***
Timeslot 0 Bit 4
E2i
VIH VIL t8OD VOH VOL t8OL t8OT t8OT t8OH t8OT t8OD t8OD
E8Ko
Figure 24 - E8Ko Timing AC Electrical Characteristics - CEPT Link Timing (Figures 25 and 26) Characteristics 1 2 3 4 5 6 7 8 Transmit Steering Delay* Transmit Steering Transition Time E2i Clock Period E2i Clock Width High or Low Receive Data Setup Time Receive Data Hold Time Receive Steering Setup Time Receive Steering Hold Time Sym. tTSD tTST tPEC tWEC tRDS tRDH tRSS tRSH 400 200 30 40 30 40 488 244 Min. 25 Typ. Max. 150 40 600 Units ns ns ns ns ns ns ns ns Test Conditions 200 pF load 200 pF load
Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * The difference between tTSD for TxA and TxB is not greater than 20 ns.
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Zarlink Semiconductor Inc.
MT8979
Data Sheet
Transmitted CEPT Link Bit Cells
Bit Cell
C2i
VIH VIL tTSD tTST tTSD tTST
TxA or TxB
VOH VOL
Figure 25 - Transmit Timing for CEPT Link
Received CEPT Link Bit Cells tWEC E2i VIH VIL tRDS VIH VIL tRSS RxA or RxB VIH VIL
Bit Cells tPEC tWEC
tRDH
RxD
tRSH
Figure 26 - Receive Timing for CEPT Link
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Zarlink Semiconductor Inc.
MT8979
Appendix
Control and Status Register Summary 7
UNUSED Keep at 1
Data Sheet
6
LOOP16 1 Enabled 0 Disabled
5
UNUSED Keep at 1
4
3
NDBD 1 No Debounce 0 Debounce
2
NDBC 1 No Debounce 0 Debounce
1
NDBB 1 No Debounce 0 Debounce
0
NDBA 1 No Debounce 0 Debounce
Master Control Word 1 (MCW1) - CSTi0, Channel 15
UNUSED Keep at 1 UNUSED Keep at 0 CCS 1 Common Channel 0 Channel Associated 8 kHz SEL 1 Enabled 0 Disabled TXAIS 1 Alarm On 0 Alarm Off TXTS16AIS 1 Alarm On 0 Alarm Off XCTL 1 Set High 0 Cleared UNUSED
Master Control Word 2 (MCW2) - CSTi0, Channel 31
UNUSED Keep at 0 SiMUX 1 Enabled 0 Disabled RMLOOP 1 Enabled 0 Disabled HDB3en 1 Disabled 0 Enabled Maint 1 Enabled 0 Disabled CRCen 1 Enabled 0 Disabled DGLOOP 1 Enabled 0 Disabled ReFR Device reframes on High to Low Transition
Master Control Word 3 (MCW3) - CSTi1, Channel 18
DATA 1 No ADI 0 Enable ADI LOOP 1 Enabled 0 Disabled RxPAD4 RxPAD2 RxPAD1 TxPAD4 TxPAD2 TxPAD1
Per Channel Cotnrol Word - CSTi0, Channels 0-14 and 16-30
A(N) Tx Signalling Bit B(N) Tx Signalling Bit C(N) Tx Signalling Bit D(N) Tx Signalling Bit A(N + 15) Tx Signalling Bit B(N + 15) Tx Signalling Bit C(N + 15) Tx Signalling Bit D(N + 15) Tx Signalling Bit
Channel Associated Signalling - CSTi1, Channels N = 1 to 15
IUO Should be kept at 1 FAF2-8 Frame Alignment Signal - Keep at "0011011"
Frame Alignment Signals - CSTi1, Channel 16
MA1-4 Multiframe Alignment Signal - Keep at "0000" X1 Spare Bit Should be 1 Y 1 Alarm On 0 Alarm Off X2, X3 Spare Bits - Should be 1
Multiframe Alignment Signals - CSTi1, Channel 0
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Zarlink Semiconductor Inc.
MT8979
IU1 Reserved for International Use NFAF Keep at "1" ALM 1 Alarm On 0 Alarm Off NU1-5 Bits Reserved for National Use - Should be kept at "1"
Data Sheet
Non-Frame Alignment Signal - CSTi1, Channel 17 7
TFSYN 1 Out of Sync 0 In Sync
6
MFSYN 1 Out of Sync 0 In Sync
5
ERR Frame Alignment Signal Error Count
4
SLIP Changes State when Slip Performed
3
RXAIS 1 Alarm Detected 0 No Alarm
2
TXTS16AIS 1 Alarm Detected 0 No Alarm
1
XS 1 XSt High 0 XSt Low
0
UNUSED
Master Control Word 1 (MSW1) - CSTo, Channel 18
Si2 Remote SMF2 is: 1 Correct 0 Errored Si1 Remote SMF1 is: 1 Correct 0 Errored UNUSED CRC Timer Transition from 1 to 0 indicates start of CRC Error Counter CRC Ref 1 Reframed forced by lack of CRC frame CRC Sync 1 CRC Frame not Detected 0 CRC Frame Detected FrmPhase Bit 8 of Phase Status Word
Master Status Word 2 (MSW2) - CSTo, Channel 21
TxTSC Transmit Timeslot Count, Timeslots between F0i and E8Ko TxBTC Transmit Bit Count - bit positions within TxTSC between F0i and E8Ko
Phase Status Word - CSTo, Channel 19
CERC 0 - 7 Bits 0 - 7 of CRC Error Counter
CRC Error Counter - CSTo, Channel 20
A(N) Rx Signalling Bit B(N) Rx Signalling Bit C(N) Rx Signalling Bit D(N) Rx Signalling Bit A(N + 15) Rx Signalling Bit B(N + 15) Rx Signalling Bit C(N + 15) Rx Signalling Bit D(N + 15) Rx Signalling Bit
Received Channel Associated Signalling - CSTo, Channels N = 1 to 15
IUO International Bit FAF2-8 Received Frame Alignment Signal
Received Frame Alignment Signals - CSTo, Channel 16
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Zarlink Semiconductor Inc.
MT8979
MA1-4 Received Multiframe Alignment Signal X1 International Bit Y 1 Remote MF Lost 0 Remote MF Detected
Data Sheet
X2, X3 International Bits
Received Multiframe Alignment Signals - CSTo, Channel 0
IU1 Reserved for International Use NFAF ALM 1 Detected 0 Not Detected NU1-5 Received Bits Reserved for National Use
Received Non-Frame Alignment Signal - CSTo, Channel 17
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Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2005. All rights reserved.
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ISSUE ACN DATE APPRD.
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